Sense amplifiers are widely known in the art and are commonly employed in many types of integrated circuits such as random access semiconductor memory devices containing a plurality of rows and columns of memory cells to detect and amplify the signals that are generated by the memory cells.
To access a particular group of memory cells, i.e. a word, located within a memory array, the addresses of both the row and the columns to which the memory cell group is coupled must first be decoded. For example in a Static Random Access Memory (SRAM) array, each cell in the array is connected to two "bitlines", one the complement of the other. These two bitlines, known as the "true" and "complement" bitlines, together comprise a column, the address of which must be decoded in order to read or write the state of any one cell connected to the column. In high performance random access memories, prior to carrying out a read operation, load resistors or some other mechanism precharges the bitlines so as to equalize the voltages thereon. Thereafter, the memory cell is coupled to the bitlines allowing the current supplied by an SRAM memory cell to modify the bitline voltages. The true and the complement bitlines are, in turn, coupled to the input leads of a sense amplifier which senses the changes in the bitline voltages and in response thereto generates a voltage signal representative of the data stored in the memory cell.
As CMOS processing fabrication technologies improve, Integrated Circuits (ICs) are produced having transistors with thinner gate oxides and ever decreasing channel dimensions. As a result, the maximum allowable voltage supply that can be reliably applied to such ICs decreases. Additionally, as memories become more dense, the current supplied by an SRAM cell to the bitlines in the memory array decreases. This decrease may result in slower charging and discharging of the true and the complement bitlines with an attendant delay in the readout of data from the sense amplifier. Therefore, a high-density, high-performance random access memory must have a sense amplifier which can operate effectively at a small voltage, e.g. 2.5 V, and must minimize the response time to the small differential signals of the array bitlines.
FIG. 1 of commonly invented U.S. Pat. No. 5,585,747, incorporated herein by reference in its entirety, shows a transistor level schematic diagram of a sense amplifier which is very fast and consumes very low power. This amplifier preferably requires a voltage supply exceeding a sum consisting of three transistor threshold voltages plus the differential voltage generated at the output terminals of the amplifier.
As the IC technology advances, device operating voltages decrease faster than the threshold voltages of MOS transistors. As a result, circuits that operate effectively at higher voltage supplies may fail at lower voltage supplies. Therefore a need exists for a sense amplifier which provides a fast response time even when powered by a lower voltage supply.
A sense amplifier often does not generate output voltage signals capable of reaching the limits of a positive and a negative voltage supply. To ensure a fast response time, a sense amplifier often generates a differential output voltage signal that is substantially smaller than the voltage supply. To generate an output voltage signal capable of reaching the voltage supply limits (a rail-to-rail output signal), the differential output voltage of a sense amplifier is typically applied to input terminals of an output amplifier which further amplifies the signal to generate a rail-to-rail output voltage signal.
FIG. 1 illustrates a known two-stage amplifier having a sense amplifier 60 and an output amplifier 70. Sense amplifier 60 receives differential input voltage signals at its input terminals IN1 and IN2 and generates differential output voltage signals at its output terminals OUT1 and OUT2. To provide signal amplification, the ratio of the channel width to the channel length, i.e. W/L (the aspect ratio) of transistors 14 and 15 must be greater than that of transistors 16 and 17, respectively, otherwise sense amplifier 60 does not continuously respond to the changing differential input voltage but instead operates as a latch, latching the positive or negative differential input voltage signal present when signal ENABLE is asserted.
The relatively small differential output voltage generated across output terminals OUT1 and OUT2, e.g. 600 mv, of sense amplifier 60, is subsequently applied to input terminals IN4 and IN3 of output amplifier 70. If the voltage signal applied to input terminal IN3 is greater than that applied to input terminal IN4, the saturated current I3 flowing through transistor 18 exceeds the saturated current I4 flowing through matched transistor 19. Transistor 21 is matched and mirrored to transistor 20 (i.e. transistor 21 has the same size, the same source voltage and the same gate voltage as that of transistor 20) to provide the same saturated current flow through transistor 21 as that through transistor 20 which, in turn, is equal to the current through transistor 18. With the saturated current of transistor 21 therefore exceeding that of transistor 19, the output node OUT switches to a voltage close to that of the positive voltage supply. If, on the other hand, the voltage signal applied to input terminal IN3 is smaller than that applied to input terminal IN4, the saturated current flow through transistors 18, 20 and 21 decreases and that through transistor 19 increases. With the saturated current of transistor 19 exceeding that of transistor 21, terminal OUT is pulled to a voltage slightly above the voltage at the source terminals of transistors 18 and 19, which is near ground. Therefore, the signal at output terminal OUT varies almost from rail-to-rail depending on whether the voltage at terminal IN3 is greater or smaller than that at terminal IN4.
A first disadvantage of output amplifier 70 is that it consumes a relatively high current.
A second disadvantage of output amplifier 70 is that it has a relatively slow response, rendering output amplifier 70 undesirable for use in a data read path of a high speed IC.